(China (Mainland))
Product Summary
The CDP68HC68P1E is a serially addressed 8-bit Input/Output port that allows byte or individual bit control. It consists of three registers, an output buffer and control logic. Data is shifted in and out of the device via shift register that utilizes the SPI (Serial Peripheral Interface) bus. The I/O port data flow of the CDP68HC68P1E is controlled by the Data Direction Register and data is stored in the Data Register that outputs or senses the logic levels at the buffered I/O pins. All inputs, including the serial interface are Schmitt triggered.
Parametrics
CDP68HC68P1E absolute maximum ratings: (1)DC Supply Voltage Range, (VDD): -0.5V to +7V; (2)Input Voltage Range, All Inputs: -0.5V to VDD +0.5V; (3)DC Input Current, Any One Input: ±10mA; (4)Power Dissipation Per Package (PD): TA = -40℃ to 60℃ (Package Type E): 500mW, TA = 60℃ to 85℃ (Package Type E) Derate Linearly at 12mW/oC to 200mW; (5)Temperature Range (TA): Package Type E, M: -55℃ to 85℃; (6)DC Operating Voltage Range: 3V Min, 6V Max; (7)Serial Clock Frequency, fSCK, VDD = 3V: 1.05MHz Max; (8)Serial Clock Frequency, fSCK, VDD = 4.5V: 2.1MHz Max; (9)Input Voltage Range, VIH: VDD +0.3V Max; (10)Input Voltage Range, VIL: -0.3V Min.
Features
CDP68HC68P1E features: (1)Fully Static Operation; (2)Operating Voltage Range 3-6V; (3)Compatible with Intersil/Motorola SPI Bus; (4)2 External Address Pins Tied to VDD or VSS to Allow Up to 4 Devices to Share the Same Chip Enable; (5)Versatile Bit-Set and Bit-Clear Capability; (6)Accepts Either SCK Clock Polarity - SCK Voltage Level is Latched When Chip Enable Goes Active; (7)All Inputs are Schmitt-Trigger; (8)8-Bit I/O Port - Each Bit can be Individually Programmed as an Input or Output Via an 8-Bit Data Direction Register; (9)Programmable On Board Comparator; (10)Simultaneous Transfer of Compare Information to CPU During Read or Write - Separate Access Not Required.
Diagrams
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